AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 506

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 24-6.
1.
32117C–AVR-08/11
Offset
0xAC
0xBC
0x9C
0xA0
0xA4
0xA8
0xB0
0xB4
0xB8
0xC0
0xC4
0xFC
0x94
0x98
The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
MACB Register Memory Map (Continued)
Specific Address 1 Bottom Register
Specific Address 2 Bottom Register
Specific Address 3 Bottom
Specific Address 4 Bottom
Transmit Pause Quantum
Specific Address 1 Top Register
Specific Address 2 Top
Specific Address 3 Top
Specific Address 4 Top Register
Type ID Checking Register
User Input/output
Statistics registers (PFR to TPF) should be read frequently enough to prevent loss of data. The
receive statistics registers are only incremented when the receive enable bit is set in the network
control register (NCR.RE). Write access to statistics registers is allowed if NCR.WESTAT is set.
Statistic registers are cleared on a read and stick at all ones when they count to their maximum
value.
Wake on LAN
Hash Register Top
Version Register
Register
Register
Register
Register
Register
Register
Register
Register
Register Name
VERSION
USRIO
SA1B
SA1T
SA2B
SA2T
SA3B
SA3T
SA4B
SA4T
WOL
HRT
TPQ
TID
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Access
AT32UC3C
0x0000FFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
(1)
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