AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 105

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

9.3 Frame Buffer
9.3.1 Data Management
8321A–MCU Wireless–10/11
The Atmel AT86RF232 contains a 128 byte dual port SRAM. One port is connected to
the SPI interface, the other to the internal transmitter and receiver modules. For data
communication, both ports are independent and simultaneously accessible.
The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the
radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum
length at a time.
Frame Buffer access modes are described in
conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR).
Frame Buffer access is only possible if the digital voltage regulator (DVREG) is turned
on. This is valid in all device states except in SLEEP state. An access in P_ON state is
possible if pin 17 (CLKM) provides the 1MHz master clock.
Data in Frame Buffer (received data or data to be transmitted) remains valid as long as:
 No new frame or other data are written into the buffer over SPI
 No new frame is received (in any BUSY_RX state)
 No state change into SLEEP state is made
 No RESET took place
By default there is no protection of the Frame Buffer against overwriting. Therefore, if a
frame is received during Frame Buffer read access of a previously received frame,
interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten.
Even so, the old frame data can be read, if the SPI data rate is higher than the effective
over air data rate. For a data rate of 250kb/s a minimum SPI clock rate of 1MHz is
recommended. Finally the microcontroller should check the transferred frame data
integrity by an FCS check.
To protect the Frame Buffer content against being overwritten by newly incoming
frames the radio transceiver state should be changed to PLL_ON state after reception.
This can be achieved by writing immediately the command PLL_ON to register bits
TRX_CMD (register 0x02, TRX_STATE) after receiving the frame, indicated by
IRQ_3 (TRX_END).
Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames
against overwriting, for details refer to
Both procedures do not protect the Frame Buffer from overwriting by the
microcontroller.
In Extended Operating Mode during TX_ARET operation, see
transceiver switches to receive, if an acknowledgement of a previously transmitted
frame was requested. During this period received frames are evaluated, but not stored
in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement
frame and retry the frame transmission without writing them again.
Note:
1.
The IRQ_6 (TRX_UR) interrupt also occurs on the attempt to write frames
longer than 127 octets to the Frame Buffer. In that case the content of the
Frame Buffer cannot be guaranteed.
Section
11.6.
Section
6.2.2. Frame Buffer access
Section
AT86RF232
7.2.4, the radio
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