AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 25

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

6.6 Interrupt Logic
6.6.1 Overview
Table 6-10. Interrupt Description in Basic Operating Mode.
8321A–MCU Wireless–10/11
IRQ Name
IRQ_7 (BAT_LOW)
IRQ_6 (TRX_UR)
IRQ_5 (AMI)
IRQ_4 (CCA_ED_DONE)
IRQ_3 (TRX_END)
IRQ_2 (RX_START)
IRQ_1 (PLL_UNLOCK)
IRQ_0 (PLL_LOCK)
Description
Indicates a supply voltage below the programmed threshold.
Indicates a Frame Buffer access violation.
Indicates an address match.
Multi-functional interrupt:
1. AWAKE_END:
2. CCA_ED_DONE:
RX: Indicates the completion of a frame reception.
TX: Indicates the completion of a frame transmission.
Indicates the start of a PSDU reception. Register bits TRX_STATUS changes to
BUSY_RX, the PHR is valid to be read from Frame Buffer.
Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state,
the PA is turned off immediately.
Indicates PLL lock.


The Atmel AT86RF232 differentiates between nine interrupt events (eight physical
interrupt registers, one shared by two functions). Each interrupt is enabled by setting
the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each
pending interrupt is stored in a separate bit of the interrupt status register. All interrupt
events are OR-combined to a single external interrupt signal (IRQ pin). If an interrupt is
issued,
register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to
this register clears the interrupt status register and thus the IRQ pin, too.
Interrupts are not cleared automatically when the event that caused them vanishes.
Exceptions
occurrence of one clears the other.
The supported interrupts for the Basic Operating Mode are summarized in
The interrupt handling in Extended Operating Mode is described in
Note:
Indicates finished transition to TRX_OFF state from P_ON, SLEEP, or RESET
state.
Indicates the end of a CCA or ED measurement.
pin 24 (IRQ) = H,
1.
are
The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the
transceiver enters TRX_OFF state after P_ON, or RESET, because
register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to
enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is
entered.
IRQ_0 (PLL_LOCK)
the microcontroller
and
IRQ_1 (PLL_UNLOCK)
shall
read
the
AT86RF232
Section
interrupt
because
Table
7.2.5.
Section
7.2.3.4
7.1.2.3
9.5.4
9.3.3
8.4.4
8.5.4
7.1.3
7.1.3
7.1.3
9.7.5
9.7.5
6-10.
status
the
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