AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 118

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

9.7 Frequency Synthesizer (PLL)
9.7.1 Overview
9.7.2 RF Channel Selection
9.7.3 Frequency Agility
9.7.4 Calibration Loops
118
AT86RF232
The main PLL features are:
 Generate RX/TX frequencies for all IEEE 802.15.4 – 2.4GHz channels
 Autonomous calibration loops for stable operation within the operating range
 Two PLL-interrupts for status indication
 Fast PLL settling to support frequency hopping
The PLL generates the RF frequencies for the Atmel AT86RF232. During receive
operation the frequency synthesizer works as a local oscillator on the radio transceiver
receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is
directly modulated to generate the RF transmit signal. The frequency synthesizer is
implemented as a fractional-N PLL.
Two calibration loops ensure correct PLL functionality within the specified operating
limits.
The PLL is designed to support 16 channels in the 2.4GHz ISM band with channel
spacing of 5MHz according to IEEE 802.15.4. The center frequency of these channels
is defined as follows:
where k is the channel number.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
When the PLL is enabled during state transition from TRX_OFF to PLL_ON, the settling
time is typically t
and PLL self calibration, refer to
indicated with an interrupt IRQ_0 (PLL_LOCK).
Switching between 2.4GHz ISM band channels in PLL_ON or RX_ON states is typically
done within t
frequency hopping applications.
When starting the transmit procedure the PLL frequency is changed to the transmit
frequency within a period of t
transmission the PLL settles back to the receive frequency within a period of
t
or IRQ_1 (PLL_UNLOCK) within these periods.
Due to variation of temperature, supply voltage and part-to-part variations of the radio
transceiver the VCO characteristics may vary.
To ensure a stable operation, two automated control loops are implemented, center
frequency (CF) tuning and delay cell (DCU) calibration. Both calibration loops are
initiated automatically when the PLL is enabled during state transition from TRX_OFF to
PLL_ON state. Additionally, center frequency calibration is initiated when the PLL
changes to a different channel center frequency.
TX_RX
= 32µs. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK)
Fc [MHz] = 2405 + 5 x (k – 11), for k = 11, 12, ..., 26
PLL_SW
TR4
= 80µs, including settling of the analog voltage regulator (AVREG)
= 11µs. This makes the radio transceiver highly suitable for
RX_TX
Table 7-2
= 16µs before starting the transmission. After the
and
Figure
13-12. A lock of the PLL is
8321A–MCU Wireless–10/11