AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 106

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

9.3.2 User accessible Frame Content
Figure 9-6. AT86RF232 Frame Structure.
9.3.3 Interrupt Handling
Frame
Duration
Access
106
0
AT86RF232
Preamble Sequence
SHR not accesible
PHY generated
Length [octets]
4 octets
A radio transceiver state change, except a transition to SLEEP, or RESET state, does
not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the
Frame Buffer is powered off and the stored data gets lost.
The Atmel AT86RF232 supports an IEEE 802.15.4 compliant frame format as shown in
Figure
A frame comprises two sections, the radio transceiver internally generated SHR field
and the user accessible part stored in the Frame Buffer. The SHR contains the
preamble and the SFD field. The variable frame section contains the PHR and the
PSDU including the FCS, see
To access the data follow the procedures described in
The frame length information (PHR field) and the PSDU are stored in the Frame Buffer.
During frame reception, the link quality indicator (LQI) value, the energy detection (ED)
value, and the status information (RX_STATUS) of a received frame are additionally
stored, see
transceiver appends these values to the frame data during Frame Buffer read access.
If the SRAM read access is used to read an RX frame, the frame length field (PHR) can
be accessed at address zero. The SHR cannot be read by the microcontroller.
For frame transmission, the PHR and the PSDU needs to be stored in the Frame
Buffer. The maximum frame size supported by the radio transceiver is 128 bytes. If the
register bit TX_AUTO_CRC_ON is set in register 0x05 (PHY_TX_PWR), the FCS field
of the PSDU is replaced by the automatically calculated FCS during frame
transmission. There is no need to write the FCS field when using the automatic FCS
generation.
To manipulate individual bytes of the Frame Buffer a SRAM write access can be used
instead.
For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the
radio transceiver is one byte (Frame Length Field + one byte of data).
Access conflicts may occur when reading and writing data simultaneously at the two
independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their
own address counter that points to the Frame Buffer’s current address.
Access violations occurs during concurrent Frame Buffer read or write accesses, when
the SPI port’s address counter value becomes higher than or equal to that of TX/RX
BBP port.
Note:
4
SFD
9-6.
1
1.
5
PHR
Stored into Frame Buffer during frame reception.
Section
6
8.6,
TX: Frame Buffer content
Section
Payload
Section
n octets (n <= 128)
RX: Frame Buffer content
8.4, and
8.2.
n + 3
Section
FCS
Section
6.2.2, respectively. The radio
n + 5
LQI
6.2.2.
(1)
n + 6
8321A–MCU Wireless–10/11
3 octets
ED
(1)
n + 7
RX_STATUS
n + 8
(1)