AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 107

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

8321A–MCU Wireless–10/11
While receiving a frame, primarily the data needs to be stored in the Atmel AT86RF232
Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer
32µs after IRQ_2 (RX_START) at the earliest. When reading the frame data
continuously the SPI data rate shall be lower than 250kb/s to ensure no under run
interrupt occurs. To avoid access conflicts and to simplify the Frame Buffer read access
Frame Buffer Empty indication may be used, for details refer to
During transmission, an access violation occurs on Frame Buffer write access, when
the SPI port’s address counter value becomes less than or equal to that of TX BBP
port.
Both these access violations may cause data corruption and are indicated by
IRQ_6 (TRX_UR) interrupt when using the Frame Buffer access mode. Access
violations are not indicated when using the SRAM access mode.
Notes:
1.
2.
3.
Interrupt IRQ_6 (TRX_UR) is valid 64µs after IRQ_2 (RX_START). The
occurrence of the interrupt can be disregarded when reading the first byte of the
Frame Buffer between 32µs and 64µs after the RX_START interrupt.
If a Frame Buffer read access is not finished until a new frame is received, an
IRQ_6 (TRX_UR) interrupt occurs. Nevertheless the old frame data can be
read, if the SPI data rate is higher than the effective PHY data rate. A minimum
SPI clock rate of 1MHz is recommended in this case. Finally, the microcontroller
should check the integrity of the transferred frame data by calculating the FCS.
When writing data to the Frame Buffer during frame transmission, the SPI data
rate shall be higher than the PHY data rate to ensure no under run interrupt.
The first byte of the PSDU data must be available in the Frame Buffer before
SFD transmission is complete, which takes 176µs (16µs PA ramp-up + 160µs
SHR) from the rising edge of pin 11 (SLP_TR) (see
Figure
Section
AT86RF232
7-2).
11.5.
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