AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 17

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

Figure 6-6. Example SPI Sequence – Register Access Mode.
6.2.2 Frame Buffer Access Mode
Figure 6-7. Packet Structure - Frame Read Access.
/SEL
SCLK
MOSI
MISO
8321A–MCU Wireless–10/11
MOSI
MISO
Register Write Access
0
byte 1 (command byte)
0
PHY_STATUS
WRITE COMMAND
PHY_STATUS
1
reserved[4:0]
On write access, the second byte transferred on MOSI contains the write data to the
selected address (see
Figure 6-5. Packet Structure - Register Write Access.
Each register access must be terminated by setting /SEL = H.
Figure 6-6
and read respectively.
The Atmel AT86RF232 128-byte Frame Buffer can hold the PHY service data unit
(PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length
at a time. A detailed description of the Frame Buffer can be found in
introduction to the IEEE 802.15.4 frame format can be found in
Frame Buffer read and write accesses are used to read or write frame data (PSDU and
additional information) from or to the Frame Buffer. Each access starts with /SEL = L
followed by a command byte on MOSI. If this byte indicates a frame read or write
access, the next byte PHR indicates the frame length followed by the PSDU data, see
Figure 6-7
On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO
starting with the second byte. After the PSDU data, three more bytes are transferred
containing the link quality indication (LQI) value, the energy detection (ED) value, and
the status information (RX_STATUS) of the received frame, for LQI details refer to
Section
access.
MOSI
MISO
byte 2 (data byte)
PHR[7:0]
WRITE DATA
XX
XX
8.6. The
1
and
illustrates a typical SPI sequence for a register access sequence for write
byte 1 (command byte)
1
PHY_STATUS
Figure
ADDRESS[5:0]
Figure 6-7
byte 3 (data byte)
6-8.
Figure
PSDU[7:0]
XX
6-5).
illustrates the packet structure of a Frame Buffer read
Register Read Access
READ COMMAND
WRITE DATA[7:0]
PHY_STATUS
byte 2 (data byte)
XX
byte n-1 (data byte)
ED[7:0]
XX
READ DATA
Section
AT86RF232
XX
RX_STATUS[7:0]
byte n (data byte)
8.1.
Section
XX
9.3. An
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