AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 178
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AT90CAN64
Manufacturer Part Number
AT90CAN64
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 17-1. USARTn Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USARTn (listed
from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all
units. The Clock Generation logic consists of synchronization logic for external clock input used
by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USARTn module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
1. Refer to
on page 79
Figure 1-2 on page 5
for USARTn pin placement.
UCSRAn
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn (Transmit)
UBRRn[H:L]
or
(1)
Figure 1-3 on page
UCSRBn
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
6,
CHECKER
PARITY
CLOCK
PARITY
DATA
Table 9-15 on page
CLKio
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
RX
83, and
PIN
TX
Receiver
UCSRCn
7679H–CAN–08/08
Table 9-10
XCKn
RxDn
TxDn
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