AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 278

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.4.1
278
AT90CAN32/64/128
Differential Channels
Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 21-7. ADC Timing Diagram, Free Running Conversion
Table 21-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs at a specific phase of CK
user (i.e., all single conversions, and the first free running conversion) when CK
take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CK
clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is
Condition
Sample & Hold (Cycles from Start of
Convention)
Conversion Time (Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
ADC Conversion Time
Complete
Prescaler
Reset
One Conversion
11
12
MUX and REFS
Update
1
13
2
Next Conversion
1
Sign and MSB of Result
LSB of Result
3
2
MUX and REFS
Update
Sample &
Hold
4
3
5
Sample & Hold
4
6
7
One Conversion
8
Conversion
9
First
14.5
25
10
Conversion
Complete
11
12
ADC2
13
Single Ended
. A conversion initiated by the
Conversion,
ADC2
Sign and MSB of Result
Normal
ADC2
LSB of Result
1.5
13
Next Conversion
is high will take 14 ADC
equal to half the ADC
1
Prescaler
Reset
2
ADC2
7679H–CAN–08/08
Conversion
Triggered
Auto
13.5
is low will
2