AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 355

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.9.2
25.9.2.1
25.9.2.2
7679H–CAN–08/08
Data Registers
Reset Register
Programming Enable Register
The data registers are selected by the JTAG instruction registers described in section
ming Specific JTAG Instructions” on page
operations are:
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset
as long as there is a high value present in the Reset Register. Depending on the Fuse settings
for the clock options, the part will remain reset for a Reset Time-out period (refer to
Sources” on page
latched, so the reset will take place immediately, as shown in
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-
tents of the register is equal to the programming enable signature, programming via the JTAG
port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when
leaving Programming mode.
Figure 25-10. Programming Enable Register
• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
• Reset Register
• Programming Enable Register
• Programming Command Register
• Flash Data Byte Register
Register. The AVR automatically alternates between reading the low and the high byte for
each new Capture-DR state, starting with the low byte for the first Capture-DR encountered
after entering the PROG_PAGEREAD command. The Program Counter is post-incremented
after reading each high byte, including the first read byte. This ensures that the first data is
captured from the first address set up by PROG_COMMANDS, and reading the last location
in the page makes the program counter increment into the next page.
38) after releasing the Reset Register. The output from this data register is not
TDO
TDI
D
A
T
A
0xA370
=
ClockDR & PROG_ENABLE
353. The data registers relevant for programming
D
Q
AT90CAN32/64/128
Figure 23-2 on page
Programming Enable
302.
“Program-
“Clock
355