AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 231
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AT90CAN64
Manufacturer Part Number
AT90CAN64
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN64-15AT
Manufacturer:
Atmel
Quantity:
3 327
Company:
Part Number:
AT90CAN64-15AT1
Manufacturer:
Atmel
Quantity:
1 985
Company:
Part Number:
AT90CAN64-15AZ
Manufacturer:
Atmel
Quantity:
1 995
Company:
Part Number:
AT90CAN64-15MT
Manufacturer:
Freescale
Quantity:
100
Company:
Part Number:
AT90CAN64-15MT1
Manufacturer:
Atmel
Quantity:
7 775
Part Number:
AT90CAN64-15MT1
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
AT90CAN64-16AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
AT90CAN64-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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18.8.6
7679H–CAN–08/08
Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from master to slave and vice versa. The master must instruct
the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multimaster sys-
tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the
master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 18-19. Combining Several TWI Modes to Access a Serial EEPROM
1. The transfer must be initiated
2. The EEPROM must be instructed what location should be read
3. The reading must be performed
4. The transfer must be finished
S
S = START
Transmitted from master to slave
SLA+W
A
Master Transmitter
ADDRESS
A
Rs = REPEATED START
Rs
Transmitted from slave to master
SLA+R
AT90CAN32/64/128
A
Master Receiver
DATA
P = STOP
A
231
P
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