AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 69
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AT90CAN64
Manufacturer Part Number
AT90CAN64
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Part Number:
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Freescale
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100
Company:
Part Number:
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Manufacturer:
MICROCHIP/微芯
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Part Number:
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Manufacturer:
MICROCHIP/微芯
Quantity:
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Part Number:
AT90CAN64-16MU
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ATMEL/爱特梅尔
Quantity:
20 000
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7679H–CAN–08/08
Figure 9-3.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay t
Figure 9-4.
Figure
INSTRUCTIONS
INSTRUCTIONS
Synchronization when Reading an Externally Applied Pin value
Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
PINxn
r16
r17
r17
pd,max
and t
pd
through the synchronizer is 1 system clock period.
out PORTx, r16
pd,min
XXX
, a single signal transition on the pin will be delayed
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
AT90CAN32/64/128
pd, min
in r17, PINx
in r17, PINx
0xFF
0xFF
69
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