ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 158
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ATmega16U4
Manufacturer Part Number
ATmega16U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2.1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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15.10.1
15.10.2
7766F–AVR–11/10
Fault Protection Trigger Source
Noise Canceler
The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alterna-
tively the Analog Comparator output can be used as trigger source for the Fault Protection unit.
The Analog Comparator is selected as trigger source by setting the Fault Protection Analog
Comparator (FPAC4) bit in the Timer/Counter4 Control Register (TCCR4D). Be aware that
changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to
clear the FPF4 flag after changing trigger source, setting edge detector or enabling the Fault
Protection.
Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sam-
pled using the same technique as for the T0 pin
also identical. However, when the noise canceler is enabled, additional logic is inserted before
the edge detector, which increases the delay by four system clock cycles. An Input Capture can
also be triggered by software by controlling the port of the INT0 pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Fault Protection Noise Canceler (FPNC4) bit in
Timer/Counter4 Control Register D (TCCR4D). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input. The noise can-
celer uses the system clock and is therefore not affected by the prescaler.
(Figure 12-1 on page
ATmega16/32U4
89). The edge detector is
158
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