ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 361
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ATmega16U4
Manufacturer Part Number
ATmega16U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2.1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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28.8
28.8.1
7766F–AVR–11/10
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 28-14. Pin Mapping Serial Programming
Figure 28-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega16U4/ATmega32U4, data is clocked on the rising edge
of SCK.
When reading data from the ATmega16U4/ATmega32U4, data is clocked on the falling edge of
SCK. See
To program and verify the ATmega16U4/ATmega32U4 in the serial programming mode, the fol-
lowing sequence is recommended (See four byte instruction formats in
Symbol
PDO
SCK
PDI
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
Figure 28-11
XTAL1 pin.
CC
- 0.3V < AVCC < V
(TQFP-64)
for timing details.
Pins
PB2
PB3
PB1
PDO
SCK
PDI
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
I/O
O
I
I
(1)
AVCC
VCC
Serial Data out
Serial Data in
Description
Serial Clock
+1.8 - 5.5V
+1.8 - 5.5V
ATmega16/32U4
(2)
ck
ck
>= 12 MHz
>= 12 MHz
Table
28-16):
361
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