ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 233
ATmega16U4
Manufacturer Part Number
ATmega16U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2.1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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20.6.4
20.6.5
7766F–AVR–11/10
TWI Data Register – TWDR
TWI (Slave) Address Register – TWAR
caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 20-2.
To calculate bit rates, see
used in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TWPS1
0
0
1
1
TWD7
TWA6
TWI Bit Rate Prescaler
R/W
R/W
7
1
7
1
TWD6
TWA5
R/W
R/W
TWPS0
0
1
0
1
6
1
6
1
“Bit Rate Generator Unit” on page
TWD5
TWA4
R/W
R/W
5
1
5
1
TWD4
TWA3
R/W
R/W
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWA2
R/W
R/W
3
1
3
1
TWD2
TWA1
R/W
R/W
2
1
2
1
TWD1
TWA0
229. The value of TWPS1..0 is
R/W
R/W
ATmega16/32U4
1
1
1
1
TWGCE
TWD0
R/W
R/W
0
1
0
0
TWDR
TWAR
233
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