SAM3U2E Atmel Corporation, SAM3U2E Datasheet - Page 1058

• Manufacturer Part Number: SAM3U2E
• Manufacturer: Atmel Corporation

Specifications of SAM3U2E

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 57
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 5
• Twi (i2c): 2
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.5.17
Name:
Addresses: 0x400B004C [0], 0x400B0074 [1], 0x400B009C [2], 0x400B00C4 [3]
Access:
Reset:
• SRC_DSCR
0: Source address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the source.
• DST_DSCR
0: Destination address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the destination.
• FC
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
• SRC_INCR
1058
31
23
15
–
–
–
7
–
SRC_INCR
SAM3U Series
DMAC Channel x [x = 0..3] Control B Register
000
001
010
011
FC
00
10
DMAC_CTRLBx [x = 0..3]
Read-write
0x00000000
IEN
30
22
14
–
6
–
FC
Peripheral-to-Peripheral
Type of addressing mode
Memory-to-Peripheral
Peripheral-to-Memory
Memory-to-Memory
INCREMENTING
Type of transfer
29
21
13
–
5
–
FIXED
DST_INCR
DST_DSCR
28
20
12
–
4
–
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Flow Controller
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
25
17
–
9
–
1
–
SRC_INCR
6430E–ATARM–29-Aug-11
SRC_DSCR
24
16
8
–
0
–