SAM3U2E Atmel Corporation, SAM3U2E Datasheet - Page 41
SAM3U2E
Manufacturer Part Number
SAM3U2E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2E
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.7
10.8
10.9
10.10 Real-time Clock
10.11 General-Purpose Back-up Registers
10.12 Nested Vectored Interrupt Controller
6430E–ATARM–29-Aug-11
Watchdog Timer
SysTick Timer
Real-time Timer
• 16-bit key-protected once-only Programmable Counter
• Windowed, prevents the processor from being in a dead-lock on the watchdog access
• 24-bit down counter
• Self-reload capability
• Flexible system timer
• Real-time Timer, allowing backup of time with different accuracies
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Eight 32-bit general-purpose backup registers
• Thirty maskable interrupts
• Sixteen priority levels
• Dynamic reprioritization of interrupts
• Priority grouping
• Support for tail-chaining and late arrival of interrupts.
• Processor state automatically saved on interrupt entry, and restored on
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system
– selection of preempting interrupt levels and non preempting interrupt levels.
– back-to-back interrupt processing without the overhead of state saving and
– interrupt exit, with no instruction overhead.
restoration between interrupts.
SAM3U Series
41
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