SAM3U2E Atmel Corporation, SAM3U2E Datasheet - Page 187
SAM3U2E
Manufacturer Part Number
SAM3U2E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2E
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.20.7
• SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not
waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an
• SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
• SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
6430E–ATARM–29-Aug-11
31
23
15
7
System Control Register
Reserved
30
22
14
6
The SCR controls features of entry to and exit from low power state. See the register summary
in
Table 13-30 on page 178
29
21
13
5
SEVONPEND
SEV
28
20
12
instruction or an external event.
4
for its attributes. The bit assignments are:
Reserved
Reserved
Reserved
Reserved
27
19
11
3
SLEEPDEEP
26
18
10
2
SLEEONEXIT
SAM3U Series
25
17
9
1
Reserved
24
16
8
0
187
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