SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 148
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM4S
SAM4S
SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax
op{X}{cond} Rd, Rn, Rm
where:
op
cond
Rd
Rn, Rm
Operation
The
halfwords in each operand. This instruction:
The
ment signed integers. This instruction:
Restrictions
In these instructions:
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
Examples
SMUAD
SMUADX R3, R7, R4
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit multiplications.
• Adds the two multiplication results together.
• Writes the result of the addition to the destination register.
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit multiplications.
• Subtracts the result of the top halfword multiplication from the result of the bottom halfword
• Writes the result of the subtraction to the destination register.
• Do not use SP and do not use PC.
multiplication.
SMUSD
SMUAD
R0, R4, R5
instruction interprets the values from the first and second operands as two’s comple-
instruction interprets the values from the first and second operands as two signed
is one of:
SMUAD
SMUADX
SMUSD
SMUSDX
If
If the
is an optional condition code, see
is the destination register.
are registers holding the first and the second operands.
X
is present, the multiplications are bottom × top and top × bottom.
X
Signed Dual Multiply Add.
Signed Dual Multiply Subtract.
is omitted, the multiplications are bottom × bottom and top × top.
Signed Dual Multiply Add Reversed.
Signed Dual Multiply Subtract Reversed.
; Multiplies bottom halfword of R4 with the bottom
; halfword of R5, adds multiplication of top halfword
; of R4 with top halfword of R5, writes to R0
; Multiplies bottom halfword of R7 with top halfword
“Conditional Execution”
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
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