SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 480

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.1.5.4
26.1.5.5
480
480
SAM4S
SAM4S
Main Clock Oscillator Selection
Main Clock Frequency Counter
When enabling the main oscillator, the user must initiate the main oscillator counter with a value
corresponding to the startup time of the oscillator. This startup time depends on the crystal fre-
quency connected to the oscillator.
When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main
oscillator, the XIN and XOUT pins are automatically switched into oscillator mode and
MOSCXTS bit in the Power Management Controller Status Register (PMC_SR) is cleared and
the counter starts counting down on the slow clock divided by 8 from the MOSCXTCNT value.
Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid.
Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor.
The user can select either the 4/8/12 MHz Fast RC oscillator or the 3 to 20 MHz Crystal or
Ceramic Resonator-based oscillator to be the source of Main Clock.
The advantage of the 4/8/12 MHz Fast RC oscillator is that it provides fast startup time, this is
why it is selected by default (to start up the system) and when entering Wait Mode.
The advantage of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is that it is very
accurate.
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register
(CKGR_MOR). The switch of the Main Clock source is glitch free, so there is no need to run out
of SLCK, PLLACK or PLLBCK in order to change the selection. The MOSCSELS bit of the
Power Management Controller Status Register (PMC_SR) allows knowing when the switch
sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.
The device features a Main Clock frequency counter that provides the frequency of the Main
Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after
the next rising edge of the Slow Clock in the following cases:
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main
Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can
be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during
16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20
MHz Crystal or Ceramic Resonator-based oscillator can be determined.
• when the 4/8/12 MHz Fast RC oscillator clock is selected as the source of Main Clock and
• when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the
• when the Main Clock Oscillator selection is modified
• when the RCMEAS bit of CKGR_MFCR is written to 1.
when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit
is set)
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11