SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 910

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 36-5.
910
910
Period Value
(
PWM_CPRDUPDx)
SAM4S
SAM4S
Summary of the Update of Registers of Synchronous Channels
Thus writing these fields of a synchronous channel has no effect on the output waveform of this
channel (except channel 0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled
together by enabling the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way,
they are all disabled together by disabling channel 0 (by the CHID0 bit in PWM_DIS register).
However, a synchronous channel x different from channel 0 can be enabled or disabled inde-
pendently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the
bit SYNCx to 1 while it was at 0) is allowed only if the channel is disabled at this time (CHIDx = 0
in
a synchronous channel (by writing the SYNCx bit to 0 while it was 1) is allowed only if the chan-
nel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three meth-
ods to update the registers of the synchronous channels:
• Method 1 (UPDM = 0): the period value, the duty-cycle values and the dead-time values must
• Method 2 (UPDM = 1): the period value, the duty-cycle values, the dead-time values and the
• Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of
PWM_SR register)
be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPDx).The update is triggered at the next PWM period as
soon as the bit UPDULOCK in the
(PWM_SCUC) is set to 1 (see
trigger of the update” on page
update period value must be written by the CPU in their respective update registers
(respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPD). The update of the
period value and of the dead-time values is triggered at the next PWM period as soon as the
bit UPDULOCK in the
to 1. The update of the duty-cycle values and the update period value is triggered
automatically after an update period defined by the field UPR in the
Update Period Register”
and automatic trigger of the update” on page
ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see
3: Automatic write of duty-cycle values and automatic trigger of the update” on page
The user can choose to synchronize the PDC transfer request with a comparison match (see
Section 36.6.3 “PWM Comparison
register.
UPDM=0
. In the same way, defining a channel as an asynchronous channel while it is
“PWM Sync Channels Update Control Register”
(PWM_SCUP) (see
the bit UPDULOCK is set to 1
911).
next PWM period as soon as
“Method 1: Manual write of duty-cycle values and manual
Update is triggered at the
Units”), by the fields PTRM and PTRCS in the PWM_SCM
“PWM Sync Channels Update Control Register”
Write by the CPU
UPDM=1
912).
“Method 2: Manual write of duty-cycle values
“PWM Sync Channels
(PWM_SCUC) is set
UPDM=2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
“Method
913).