SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 85
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11.6.3.4
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
ASR
LSR
Shift Operations
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value
is used by the instruction. However, the contents in the register Rm remains unchanged. Speci-
fying a register with shift also updates the carry flag when used with certain instructions. For
information on the shift operations and how they affect the carry flag, see
Operand”
Register shift operations move the bits in a register left or right by a specified number of bits, the
shift length. Register shift can be performed:
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no
shift occurs. Register shift operations update the carry flag except when the specified shift length
is 0. The following sub-sections describe the various shift operations and how they affect the
carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is
the shift length.
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register
into the left-hand n bits of the result. See
The ASR #n operation can be used to divide the value in the register Rm by 2
being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Figure 11-7. ASR #3
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0.
See
The LSR #n operation can be used to divide the value in the register Rm by 2
regarded as an unsigned integer.
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
• during the calculation of Operand2 by the instructions that specify the second operand as a
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
destination register
register with shift. See
Figure
.
11-8.
“Flexible Second Operand”
Figure
11-7.
. The result is used by the instruction.
“Flexible Second
n
n
, with the result
, if the value is
SAM4S
SAM4S
85
85
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