SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 981

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 37-7. Data IN Transfer for Non Ping-pong Endpoint
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
USB Bus Packets
TXPKTRDY Flag
(UDP_CSRx)
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Content
Using Endpoints With Ping-pong Attribute
Set by the firmware
Data IN
PID
Prevous Data IN TX
Data IN 1
Interrupt Pending
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This
also allows handling the maximum bandwidth defined in the USB specification during bulk trans-
fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must
prepare the next data payload to be sent while the current one is being sent by the USB device.
Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
Figure 37-8. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data IN
transactions:
Cleared by Hw
Data IN 1
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
DPR access by the firmware
ACK
PID
Load In Progress
Set by the firmware
Microcontroller Load Data in FIFO
PID
Data IN
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
NAK
PID
Cleared by Firmware
USB Device
PID
DPR access by the hardware
Data IN
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
Data is Sent on USB Bus
Data IN 2
Payload in FIFO
Data IN 2
USB Bus
Cleared by Hw
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
SAM4S
SAM4S
ACK
PID
Cleared by
Firmware
Interrupt
Pending
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