SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 416
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 24-3. NAND Flash Signal Multiplexing on SMC Pins
Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used in PIO
Mode but only in peripheral mode (NWE function). If NWE function is not used for other external
memories (SRAM, LCD), it must be configured in one of the following modes.
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21of the address bus. Any bit of the address bus can also be
used for this purpose. The command, address or data words on the data bus of the NAND Flash
d e v i c e u s e th e i r o w n a d dr e s s e s w i th i n t h e N C S x a d d r es s s p a c e (c o n fi gu r e d b y
CCFG_SMCNFCS Register on the Bus Matrix User Interface). The chip enable (CE) signal of
the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then
remains asserted even when NCS3 is not selected, preventing the device from returning to
standby mode. The NANDCS output signal should be used in accordance with the external
NAND Flash device type.
Two types of CE behavior exist depending on the NAND flash device:
Figure 24-4
• PIO Input with pull-up enabled (default state after reset)
• PIO Output set at level 1
• Standard NAND Flash devices require that the CE pin remains asserted Low continuously
• This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal
during the read busy period to prevent the device from returning to standby mode. Since the
Static Memory Controller (SMC) asserts the NCSx signal High, it is necessary to connect the
CE pin of the NAND Flash device to a GPIO line, in order to hold it low during the busy period
preceding data read out.
can be directly connected to the CE pin of the NAND Flash device.
* in CCFG_SMCNFCS Matrix register
NCSx (activated if SMC_NFCSx=1) *
illustrates both topologies: Standard and “CE don’t care” NAND Flash.
SMC
NWE
NRD
NAND Flash Logic
NANDOE
NANDWE
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
NANDOE
NANDWE
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