SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 447
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SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.14.2
24.14.3
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Page Mode Restriction
Sequential and Non-sequential Accesses
NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses
within the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in
Table 24-6.
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (t
the programmed value for t
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
If the chip select and the MSB of addresses as defined in
rent access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (t
page mode, with 8-byte pages. Access to D1 causes a page access with a long access time
(t
access time (t
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
Parameter
READ_MODE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_SETUP
NRD_PULSE
NRD_CYCLE
pa
). Accesses to D3 and D7, though they are not sequential accesses, only require a short
sa
Programming of Read Timings in Page Mode
).
Value
‘x’
‘x’
t
‘x’
t
‘x’
pa
sa
pa
is shorter than the programmed value for t
sa
pa
).
) and the NRD_PULSE for accesses to the page (t
Figure 24-32
Definition
No impact
No impact
Access time of first access to the page
No impact
Access time of subsequent accesses in the page
No impact
illustrates access to an 8-bit memory device in
Table 24-5
Table
are identical, then the cur-
sa
.
24-6:
SAM4S
SAM4S
sa
), even if
447
447
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