SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 403

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 29-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
29.12 External Wait
29.12.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS2, NBS3,
A0, A1
Restriction
D[31:0]
A[25:2]
(NWE)
(NRD)
MCK
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be
set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00”
(disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT
signal delays the read or write operation in regards to the read or write controlling signal,
depending on the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode
(“Slow Clock Mode” on page
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
TDF_CYCLES = 5
read1 cycle
read1 hold = 1
(“Asynchronous Page Mode” on page
Read to Write
Wait State
409).
TDF_CYCLES = 5
4 TDF WAIT STATES
412), or in Slow Clock Mode
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
SAM9G35
SAM9G35
403
403