SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 738
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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- Download datasheet (30Mb)
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SAM9G35
SAM9G35
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
--------------------------------------------- -
--------------------------------------------------- -
------------------------------ -
---------------------------------------- -
X*CPRD*DIVA
2*X*CPRD*DIVA
X CPRD
2 X CPRD
duty cycle
duty cycle
MCK
MCK
MCK
MCK
=
=
------------------------------------------------------------------------------------------------------- -
---------------------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
or
period 2
or
--------------------------------------------- -
X*CPRD*DIVB
--------------------------------------------------- -
2*X*CPRD*DIVB
–
MCK
MCK
–
1 fchannel_x_clock
period
period 2
CDTY
CDTY
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
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