SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 458
SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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30.7.3
Name:
Address:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• NC: Number of Column Bits
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
• NR: Number of Row Bits
The reset value is 12 row bits.
458
458
DLL
NC
NR
00
01
10
11
00
01
10
11
31
23
15
–
–
–
7
SAM9G35
SAM9G35
DDRSDRC Configuration Register
DDR - Column bits
DECOD
Row bits
30
22
14
DDRSDRC_CR
0xFFFFE808
Read-write
See
–
6
10
11
12
11
12
13
14
9
Table 30-16
OCD
CAS
29
21
13
–
–
5
SDR - Column bits
10
11
8
9
NB
28
20
12
–
4
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
–
3
NR
ACTBST
26
18
10
–
–
2
DIS_DLL
25
17
–
–
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
NC
EBISHARE
DIC/DS
470.
24
16
–
8
0
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