SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 126

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.4
19.4.1
19.4.1.1
126
Arbitration
AT91SAM9G20
Arbitration Rules
Undefined Length Burst Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflicting cases
occur, in particular when two or more masters try to access the same slave at the same time.
One arbiter per AHB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user the possibility to choose between 2 arbitration types for each
slave:
This choice is made through the field ARBT of the Slave Configuration Registers
(MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration has to be done, it is realized only under specific conditions described in
Section 19.4.1 “Arbitration Rules” on page
Each arbiter has the ability to arbitrate between two or more different master’s requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix
provides specific logic in order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between
the following:
This selection can be done through the field ULBT of the Master Configuration Registers
(MATRIX_MCFG).
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
1. Idle Cycles: when a slave is not connected to any master or is connected to a master
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer is
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst (see
Burst Arbitration” on page
the current master access is too long and must be broken (see
Cycle Limit Arbitration” on page
never broken.
boundary inside INCR transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
126).
127).
126.
Section 19.4.1.1 “Undefined Length
Section 19.4.1.2 “Slot
6384E–ATARM–05-Feb-10