SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 724

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

39.4.1
Register Name: ISI_CR1
Access Type: Read-write
Reset Value: 0x00000002
• ISI_RST: Image Sensor Interface Reset
Write-only. Refer to bit SOFTRST in
0: No action
1: Resets the image sensor interface.
• ISI_DIS: Image Sensor Disable:
0: Enable the image sensor interface.
1: Finish capturing the current frame and then shut down the module.
• HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high
1: HSYNC active low
• VSYNC_POL: Vertical sYnchronization Polarity
0: VSYNC active high
1: VSYNC active low
• PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock
1: Data is sampled on falling edge of pixel clock
• EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC
1: Synchronization by embedded synchronization sequence SAV/EAV
• CRC_SYNC: Embedded Synchronization
0: No CRC correction is performed on embedded synchronization
724
CODEC_ON
CRC_SYNC
31
23
15
7
AT91SAM9G20
ISI Control 1 Register
EMB_SYNC
30
22
14
6
THMASK
Section 39.4.3 “ISI Status Register” on page 728
29
21
13
5
-
PIXCLK_POL
FULL
28
20
12
4
SFD
SLD
VSYNC_POL
27
19
11
3
-
HSYNC_POL
26
18
10
2
for soft reset status.
ISI_DIS
FRATE
25
17
9
1
6384E–ATARM–05-Feb-10
ISI_RST
24
16
8
0