SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 129

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SAM9G20

Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G20

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
19.5.1
Register Name:MATRIX_MCFG0...MATRIX_MCFG5
Access Type:Read-write
(MATRIX_MCFG5 is Write-only)
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single accesses allowing rearbitration at each beat of the INCR
burst.
2: Four Beat Burst
The undefined length burst is split into 4-beat bursts allowing rearbitration at each 4-beat burst end.
3: Eight Beat Burst
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
6384E–ATARM–05-Feb-10
31
23
15
7
Bus Matrix Master Configuration Registers
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
AT91SAM9G20
ULBT
25
17
9
1
24
16
8
0
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