ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 111

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

ST7FOXF1, ST7FOXK1, ST7FOXK2
10.3.3
Figure 52. Lite timer 2 block diagram
Functional description
Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f
counter rolls over from F9h to 00h. If f
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.
Input Capture
The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the
ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated
if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last Input Capture.
Input Capture is inhibited if the ICF bit is set.
LTIC
f
OSC
/32
LTARR
LTICR
LTCNTR
8-bit AUTORELOAD
INPUT CAPTURE
8-bit TIMEBASE
8-bit TIMEBASE
COUNTER 2
REGISTER
COUNTER 1
REGISTER
8-bit
8
8
LTCSR1
ICIE
f
LTIMER
LTCSR2
/2
ICF
0
OSC
TB
1
0
0
Timebase
1 or 2 ms
(@ 8 MHz
f
OSC
= 8 MHz, then the time period between two
TB1IE
0
)
OSC
TB1F
0
/32. An overflow event occurs when the
0
LTIC INTERRUPT REQUEST
LTTB1 INTERRUPT REQUEST
0
TB2IE
f
LTIMER
TB2F
To 12-bit AT TImer
On-chip peripherals
LTTB2
Interrupt request
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