ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 171

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

ST7FOXF1, ST7FOXK1, ST7FOXK2
Note:
Bit 1 = SSM SS Management.
Bit 0 = SSI SS Internal Mode.
SPI data I/O register (SPIDR)
Reset Value: Undefined
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
D7
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Section Slave select
management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A read to the SPIDR register returns the value located in the buffer and not the content
of the shift register (see
7
Warning:
D6
A write to the SPIDR register places data directly into the
shift register for transmission.
D5
Figure
73).
D4
Read / Write
D3
D2
On-chip peripherals
D1
171/226
D0
0