ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 44

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

Supply, reset and clock management
6.4
Note:
6.4.1
Note:
Caution:
44/226
System Integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD).
Refer to
Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V
voltage is below a V
as the power-down keeping the ST7 in reset.
The V
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when V
The LVD function is illustrated in
The voltage threshold can be enabled/disabled by option byte. See
211.
Provided the minimum V
the MCU can only be in two modes:
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull V
conditions. Refer to circuit example in
The LVD is an optional function which can be selected by option byte. See
page
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the V
device is exiting from Reset, to ensure the application functions properly.
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
V
V
Under full software control
In static safe reset
211.
IT-(LVD)
IT+(LVD)
IT-(LVD)
Section 11.2.1 on page 184
reference value for a voltage drop is lower than the V
when V
when V
IT-(LVD)
DD
DD
is falling
DD
is rising
reference value. This means that it secures the power-up as well
value (guaranteed for the oscillator frequency) is above V
Figure
for further details.
Figure 89 on page 207
16.
DD
DD
supply voltage rises monotonously when the
down to 0 V to ensure optimum restart
DD
is below:
ST7FOXF1, ST7FOXK1, ST7FOXK2
and note 4.
IT+(LVD)
Section 13.1 on page
reference value
Section 13.1 on
DD
supply
IT-(LVD)
,