ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 35

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

ST7FOXF1, ST7FOXK1, ST7FOXK2
6.1.2
Note:
Note:
Note:
These bytes are systematically programmed by ST.
Customized RC calibration
If the application requires a higher frequency accuracy or if the voltage or temperature
conditions change in the application, the frequency may need to be recalibrated. Two non-
volatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new
values. These two-byte area is Electrically Erasable Programmable Read Only Memory.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
How to program RCCRH_USER and RCCRL_USER
To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit
remains cleared). When a write access to this two-byte area occurs, the values are latched.
When RCCPGM bit is set by the software, the latched data are programmed in the
EEPROM cells. To avoid wrong programming, the user must take care to only access these
two-byte addresses.
At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared
simultaneously.
During the programming cycle, it is forbidden to access the latched data (see
Figure 9.
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
Access error handling
If a read access occurs while RCCLAT=1, then the data bus will not be driven.
If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.
RCCRH_USER and RCCRL_USER programming flowchart
CLEARED BY HARDWARE
READ MODE
RCCPGM=0
READ BYTES
RCCLAT=0
START PROGRAMMING CYCLE
RCCPGM=1 (set by software)
WRITE THE 2 BYTES
AT THEIR ADDRESS
0
WRITE MODE
RCCPGM=0
RCCLAT=1
RCCLAT=1
Supply, reset and clock management
RCCLAT
1
Figure
9).
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