73S1215F Maxim, 73S1215F Datasheet - Page 135

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

Rev. 1.4
1.4
12/16/2008
In
PRES, SEC and TEST pins.
In
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
PGADDR
(see detailed description above).”
Changed the register address for
In
In
FUSECtl bit description to TRIMPCtl.
In
In
In
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,
LEDCal and LOCKCtl registers.
In
In
report level of pin LEDn.” to the description of LEDD3, LEDD2 and
LEDD1.
In
SYCKST is set=1(STXCtl, b7=1), Rlen=max will stop the clock at the
selected (CLKLVL or SCLKLVL) level.”
In
into three primary types. These are commonly referred to as 2-wire,
3-wire and I2C synchronous cards. Each card type requires different
control and timing and therefore requires different algorithms to access.
Teridian has created an application note to provide detailed algorithms for
each card type. Refer to the application note titled 73S12xxF
Synchronous Card Design Application Note.”
In the
0V. V
application of 5V to V
set, it has no effect until V
In
In
Added
Added
Added
Formatted the document per new standard. Added section numbering.
Table
Section
Table
Table
Table
Table
Table
Table
Table
Section 1.7.15.5
Section
Table 86
Figure
DD
VccVtl.0
Section 6, Ordering
Section 7, Related
Section 8, Contact
can only be turned on by pressing the ON/OFF switch or by
1, added more description to the VCC, VPC, VDD, SCL, SDA,
5, changed “FLSHCRL” to “FLSHCTL”.
5, moved the TRIMPCtl bit description to FUSECtl and moved the
6, changed “PGADR” to “PGADDR”.
7, added PGADDR.
8, changed the reset value for RTCCtl from “0x81” to “0x00”.
23, corrected the descriptions for TCON.2 and TCON.0.
62, added “Write data controls output level of pin LEDn. Read will
26, replaced the schematic with a new schematic.
register, added “Note: the page address is shifted left by one bit
1.3.2, changed “FLSH_ERASE” to “ERASE” and
1.7.15.5, added “Synchronous card operation is broken down
and
bit description, deleted “When in power down mode, V
Table
(number 3), deleted “If CLKOFF/SCLKOFF is high and
BUS
117, changed the SYCKST bit to I2CMODE.
. If V
BUS
Information.
Documentation.
Information.
is removed and V
BUS
power is available and SCPWRDN bit is
ATRMsB
from FE21 to FE1F.
DD
will shut off.”
DD
=
135