73S1215F Maxim, 73S1215F Datasheet - Page 65

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
1.7.12 Keypad Interface
The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches)
The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches)
interface using 11 dedicated I/O pins.
interface using 11 dedicated I/O pins.
Figure 12 shows a simplified block diagram of the keypad interface.
Figure 12 shows a simplified block diagram of the keypad interface.
There are 5 drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to
rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external
resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for
a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense
(col/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce
timer. Debouncing time is adjustable through the
column scanning at an adjustable scanning rate and column scanning order through registers
and
a valid key is detected, an interrupt is generated and the valid value of the pressed key is automatically
written into
Rev. 1.4
KORDERL
KCOL Register
7
73S1215F
Keypad Interface
6
5
KCOL
4
KROW Register
3
7
/ KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When
Column Value
Keypad Clock
2
6
and
(1)
1
5
Hardware Scan Enable
0
4
Row Value
KROW
3
5
2
Keypad Clock
KSTAT Register
1
7
Figure 12: Simplified Keypad Block Diagram
0
6
registers. The keypad interface uses a 1kHz clock derived from either the
5
Scan
6
4
KORDERL / H Registers
7
7
KSIZE Register
3
6
6
2
5
Debouncing
Dividers
5
7
1
4
6
4
0
3
5
3
0
2
4
2
1
1
6
VDD
KSCAN Register
1
3
2
KSCAN
0
0
2
3
1
4
1kHz
0
5
6
register. Internal hardware circuitry performs
VDD
(2)
7
COL4:0
If smaller keypad than 6 x 5 is to be
implemented, unused row inputs
should be connected to VDD. Unused
column outputs should be left
unconnected.
(1) KCOL is normally used as Read only
register. When hardware keyscan mode
is disabled, this register is to be used by
firmware to write the column data to
handle firmware scanning.
(2) 1kHz internal clock signal can be
selected either from the PLL (= from the
12MHz main clock), or from the 32kHz
system clock.
73S1215F Data Sheet
KSCAN
65