73S1215F Maxim, 73S1215F Datasheet - Page 27

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
1.7.2
The 73S1215F contains circuitry to disable portions of the device and place it into a lower power standby
mode. This is accomplished by either shutting off the power or disabling the clock going to the block. The
miscellaneous control registers MISCtl0,
control over the power modes. There is also a device power down mode that will stop the core, clock
subsystem and the peripherals connected to it. The PWRDN bit in
power down and disable all clocks except the 32kHz oscillator. The power down mode should only be
initiated by setting the PWRDN bit in the
initiated by setting the PWRDN bit in the
various registers. Figure 5 shows how the PWRDN bit controls the various functions that comprise power
various registers. Figure 5 shows how the PWRDN bit controls the various functions that comprise power
down state.
down state.
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the
program to set the STOP bit in the
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias
circuitry, etc.). The PDMUX bit in SFR
configure the wake up interrupt logic. The power down mode is awakened from interrupts connected to
external interrupts 0, 4 and 5 (external USR[0:7], smart card, USB, RTC and Keypad). These interrupt
sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.
The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After
the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When
the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 6
shows the detailed logic for waking up the 73S1215F from a power down state using these specific interrupt
sources. Figure 7 shows the timing associated with the power down mode.
Rev. 1.4
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the
PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram.
Power Control Modes
the names of the control bits.
These are the registers and
SCVCCCtl - SCPRDN
MCLCKCtl - HOSEN
VDDFCtl - VDDFEN
MCLCKCtl - 32KEN
MISCtl1 - ANAPEN
MISCtl1 - USBPEN
MISCtl0 - PWRDN
ACOMP - CMPEN
MISCtl1 - FRPEN
PCON
Figure 5: Power Down Control
INT5Ctl
MISCtl0
MISCtl0
MISCtl1
register. This delay will enable the program to properly halt the
PWRDN Signal
SUSPEND
should be set prior to setting the PWRDN bit in order to
USB
register and not by manipulating individual control bits in
register and not by manipulating individual control bits in
and the master clock control register (MCLKCtl) provide
+
+
+
+
+
+
+
PD_ANALOG
MISCtl0
will set up the 73S1215F for
reference and bias
Smart Card Power
Analog functions
Flash Read Pulse
USB Transceiver
High Speed OSC
(suspend mode)
one-shot circuit
block references.
circuits, etc.)
These are the
(VCO, PLL,
VDDFAULT
COMPARE
ANALOG
32K OSC
73S1215F Data Sheet
27