73S1215F Maxim, 73S1215F Datasheet - Page 43

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
Serial Interface 0 Control Register (S0CON): 0x9B
Transmit and receive data are transferred via this register.
1.7.4.2
The Serial Interface 1 can operate in 2 modes:
•
•
The
Rev. 1.4
S0CON.7
S0CON.6
S0CON.5
S0CON.4
S0CON.3
S0CON.2
S0CON.1
S0CON.0
Mode A
This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start
bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to
control the parity of the serial interface: at transmission, bit TB81 in
bit, and at receive, the 9th bit affects RB81 in Special Function Register S1CON. The only difference
between Mode 3 and A is that in Mode A only the internal baud rate generator can be use to specify
baud rate.
Mode B
This mode is similar to Mode 1 of Serial interface 0. Pin RX serves as input, and TX serves as serial
output. No external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB
first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are
available by reading S1BUF, and stop bit sets the flag RB81 in the Special Function Register
S1CON. In mode 1, the internal baud rate generator is use to specify the baud rate.
S1BUF
Bit
Serial Interface 1
MSB
register is used to read/write data to/from the serial 1 interface.
SM0
Symbol
REN0
SM20
RB80
TB80
SM0
SM1
RI0
TI0
SM1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
depending on the function it performs (parity check, multiprocessor
communication etc.).
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,
RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by
software.
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software.
Table 39: The S0CON Register
Mode
SM20
th
0
1
2
3
transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
REN0
Description
8-bit UART
9-bit UART
9-bit UART
These two bits set the UART0 mode:
N/A
TB80
0x00
Function
SM0
RB80
0
0
1
1
S1CON
TI0
SM1
0
1
0
1
is outputted as the 9th
RI0
73S1215F Data Sheet
LSB
43