73S1215F Maxim, 73S1215F Datasheet - Page 72

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the
Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the
1.7.13 Emulator Port
The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, provides control of the MPU
The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, provides control of the MPU
through an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ, add
through an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ, add
trace capability to the emulator. The emulator port is compatible with the ADM51 emulators
trace capability to the emulator. The emulator port is compatible with the ADM51 emulators
manufactured by Signum Systems.
manufactured by Signum Systems.
If code trace capability is needed on this interface, 20pF capacitors (to ground) need to be added to allow
If code trace capability is needed on this interface, 20pF capacitors (to ground) need to be added to allow
the trace function capability to run properly. These capacitors should be attached to the TBUS0:3 and
the trace function capability to run properly. These capacitors should be attached to the TBUS0:3 and
ISBR signals.
ISBR signals.
1.7.14 USB Interface
1.7.14 USB Interface
The 73S1215F provides a single interface, full speed -12Mbps - USB device port as per the Universal
The 73S1215F provides a single interface, full speed -12Mbps - USB device port as per the Universal
transceiver, the Serial Interface Engine (SIE), and the data buffers. An internal pull-up to V
transceiver, the Serial Interface Engine (SIE), and the data buffers. An internal pull-up to V
indicates that the device is a full speed device attached to the USB bus (allows full speed recognition by
indicates that the device is a full speed device attached to the USB bus (allows full speed recognition by
the host without adding any external components). When using the USB interface, V
the host without adding any external components). When using the USB interface, V
3.0V – 3.6V in order to meet the USB VOH requirement. The interface is highly configurable under
3.0V – 3.6V in order to meet the USB VOH requirement. The interface is highly configurable under
firmware control. Control (Endpoint 0), Interrupt IN, Bulk IN and Bulk OUT transfers are supported. Four
firmware control. Control (Endpoint 0), Interrupt IN, Bulk IN and Bulk OUT transfers are supported. Four
endpoints are supported and are configured by firmware:
endpoints are supported and are configured by firmware:
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Figure 14 shows the simplified block diagram of the USB interface.
Figure 14 shows the simplified block diagram of the USB interface.
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Endpoint 0, the default (Control) endpoint as required by the Universal Serial Bus Specification, is
Endpoint 0, the default (Control) endpoint as required by the Universal Serial Bus Specification, is
used to exchange control and status information between the 73S1215F and the USB host.
used to exchange control and status information between the 73S1215F and the USB host.
Bulk IN Endpoint #1
Bulk IN Endpoint #1
Bulk OUT Endpoint #1
Bulk OUT Endpoint #1
Interrupt IN Endpoint #2
Interrupt IN Endpoint #2
The USB block contains several FIFOs used for communication.
The USB block contains several FIFOs used for communication.
There is a 128 byte RAM FIFO for each BULK endpoint. Maximum Bulk packet size is 64 bytes.
There is a 128 byte RAM FIFO for each BULK endpoint. Maximum Bulk packet size is 64 bytes.
There is a 32 byte RAM FIFO for the interrupt endpoint. Maximum Interrupt packet size is 16 bytes.
There is a 32 byte RAM FIFO for the interrupt endpoint. Maximum Interrupt packet size is 16 bytes.
There is a 16 byte RAM FIFO for the control endpoint. Maximum Control packet size is 16 bytes.
There is a 16 byte RAM FIFO for the control endpoint. Maximum Control packet size is 16 bytes.
D+
D-
VDD
Transceivers
MISCtl1
MISCtl1
0
1
Figure 14: USB Block Diagram
USBCon
USBPEN
USB Registers
Full Speed
Interface
12Mbps
Engine
Serial
USB
48MHz
Clock
Control Endpoint 0
Bulk IN Endpoint 1
Bulk OUT Endpoint 1
Interrupt IN Endpoint 2
128-Byte FIFO
128-Byte FIFO
16-Byte FIFO
32-Byte FIFO
DD
DD
must be between
must be between
DD
DD
on D+
on D+
Rev. 1.4