73S1215F Maxim, 73S1215F Datasheet - Page 85

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
Rev. 1.4
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high, set IO Bit low and IODir = Output.
4. Set IO Bit High and IODir = Output.
5. Set TX/RX Bit to RX mode.
6. Reload Rlength Counter.
7. Clear CLK Stop and CLK Stop level.
RLength Interrupt
CLK Stop Level
RLength Count
TX/RX Mode Bit
(Rlength = 9)
Figure 23: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode
Figure 24: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high in Interrupt routine.
4. Set TX/RX Bit to TX mode.
5. Reload Rlength Counter.
6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.
7. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
TX = '1'
RLength Count - was set for length of ATR
RLength Interrupt
CLK Stop Level
CLK Stop
TX/RX Mode Bit
generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.
IODir Bit
IO Bit
CLK
TX = '1'
Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to
IO
CLK Stop
IODir Bit
IO Bit
Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to
CLK
IO
I2CMode = 1: Data to/from Card
I2CMode = 0: Data from TX fifo
Data from Card -end of ATR
generate the Stop bit in Synchronous Mode.
1
RLength Count MAX
1
I2CMode = 1:ACK Bit (to/from card)
2
I2CMode = 0: Data from TX fifo
Count MAX
RLength
3
2
3
4
5
6
6
RLen=0
7
Rlen=1
Data from TX FIFO
4
START Bit
STOP Bit
73S1215F Data Sheet
5
6
Min ½ ETU
7
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