73S1215F Maxim, 73S1215F Datasheet - Page 81

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing,
if a parity error is detected by the 73S1215F during message reception, an error signal (BREAK) will be
generated to the smart card. The byte received will be discarded and the firmware notified of the error.
Break generation and receive byte dropping can be disabled under firmware control. During the
transmission of a byte, if an error signal (BREAK) is detected, the last byte is retransmitted again and the
firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an
interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns
are detected by the hardware and reported via an interrupt. During transmission of a message, the
firmware will write bytes into the transmit FIFO. The hardware will send them to the smart card. When the
last byte of a message has been written, the firmware will need to set the LASTTX bit in the
This will cause the hardware to insert the CRC/LRC if in a T=1 protocol mode. CRC/LRC
generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart
function to go into receive mode after this last transmit data byte if it expects a response from the smart
card. At the end of the smart card response, the firmware will put the interface back into transmit mode if
appropriate.
The hardware can check for the following card-related timeouts:
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•
•
The firmware will load the Wait Time registers with the appropriate value for the operating mode at the
appropriate time. Figure 20 shows the guard, block, wait and ATR time definitions. If a timeout occurs,
an interrupt will be generated and the firmware can take appropriate recovery steps. Support is provided
for adding additional guard times between characters (Extra Guard Time register) and between the last
byte received by the 73S1215F and the first byte transmitted by the 73S1215F Block Guard Time register
(BGT). Other than the protocol checks described above, the firmware is responsible for all protocol
checking and error recovery.
Rev. 1.4
Character Waiting Time (CWT)
Block Waiting Time (BWT)
Initial Waiting Time (IWT)
SCSCLK(5:0)
MCLK =
96MHz
PLL
SCSel(3:2)
SCCLK(5:0)
F/D Register
Figure 19: Smart Card CLK and ETU Generation
Pre-Scaler
Pre-Scaler
6 bits
6 bits
1/13
1/13
FDReg(7:4)
7.38M
7.38M
FDReg(3:0)
7.38M
MSCLKE
MSCLK
ETU Divider
FI Decoder
12 bits
1/744
Defaults
in Italics
DIV
DIV
by
by
2
2
9926
3.69M
3.69M
ETUCLK
73S1215F Data Sheet
SYNC
SCLK
CLK
CENTER
EDGE
STXCtl
SFR.
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