TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 114

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.
9.3.2 Event counter mode
9.3.3 Window mode
TC2 pin input
Counter
TC2DR
INTTC2 interrupt
pared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the
counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is
cleared.
the falling edge after the match of TC2DR and up counter.
for both the “H” and “L” levels of the pulse width.
(Window pulse) is “H” level. The contents of TC2DR are compared with the contents of up counter. If a match
found, an INTTC2 interrupt is generated, and the up-counter is cleared.
by the TC2CR<TC2CK>.
In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are com-
Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at
The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required
In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input
The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock
Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL
mode, the timer should be halted by setting TC2CR<TC2S> to "0" before the SLOW/SLEEP mode is entered.
Table 9-2 Timer/Counter 2 External Input Clock Pulse Width
Timer start
“H” width
“L” width
LDW
DI
SET
EI
LD
LD
Figure 9-3 Event Counter Mode Timing Chart
0
1
(TC2DR), 640
(EIRE). 6
(TC2CR), 00011100B
(TC2CR), 00111100B
NORMAL1/2, IDLE1/2 mode
2
2
2
3
3
/fc
/fc
n
Page 97
Minimum Input Pulse Width [s]
3
;Enables INTTC2 interrupt
; IMF= “1”
; TC2 source vclock / mode select
; Starts TC2
; Sets TC2DR
; IMF= “0”
Match detect
SLOW1/2, SLEEP1/2 mode
2
2
3
3
n
/fs
/fs
0
Counter clear
1
2
TMP86PM49UG
3