TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 216

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.5.1 Acknowledgement mode specification
16.5.1.1 Acknowledgment mode (ACK = “1”)
16.5.1.2 Non-acknowledgment mode (ACK = “0”)
Table 16-1 SCL and SDA Pins Status in Acknowledgement Mode
MST
TRX
AAS
AD0
LRB
PIN
BB
AL
Master
Mode
Slave
a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge
signal. In a slave mode, a clock is counted for the acknowledge signal.
the receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low
level generation an acknowledge signal during additional clock pulse cycle.
when a “GENERAL CALL” is received, the SDA pin is set to low level generating an acknowledge sig-
nal. After the matching of slave address or the detection of “GENERAL CALL”, in the transmitter, the
SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock
pulse cycle. In a receiver, the SDA pin is set to low level generation an acknowledge signal during addi-
tional clock pulse cycle after the matching of slave address or the detection of “GENERAL CALL”
“0”.
To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to “1”. When
In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from
In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or
The Table 16-1 shows the SCL and SDA pins status in acknowledgment mode.
To set the device as a non-acknowledgement mode, the ACK (Bit4 in SBICRA) should be cleared to
Master/slave selection status
monitor
Transmitter/receiver selection
status monitor
Bus status monitor
Interrupt service requests sta-
tus monitor
Arbitration lost detection monitor
Slave address match detection
monitor
"GENERAL CALL" detection
monitor
Last received bit monitor
SDA
When slave address matches
or a general call is detected
After matching of slave
address or general call
SDA
SCL
SCL
Pin
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
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Slave
Master
Receiver
Transmitter
Bus free
Bus busy
Requesting interrupt service
Releasing interrupt service request
–
Arbitration lost detected
-
Detect slave address match or "GENERAL CALL"
-
Detect "GENERAL CALL"
Last receive bit is "0"
Last receiv bit is "1"
Released in order to receive
an acknowledge signal.
Released in order to receive
an acknowledge signal.
A clock is counted for the acknowledge signal.
Transmitter
An additional clock pulse is generated.
–
Set to low level generating an
acknowledge signal
Set to low level generating an
acknowledge signal.
Set to low level generating an
acknowledge signal.
Receiver
TMP86PM49UG
Read
only