TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 88

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

6.3.4 Address Trap Reset
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
24/fc [s] (1.5 µs @ fc = 16.0 MHz).
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
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TMP86PM49UG