TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 143

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

11.1 Configuration
11.3.2 8-Bit Event Counter Mode (TC5, 6)
11.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)
TC6CR<TC6S>
Internal
Source Clock
Counter
TTREG6
INTTC6 interrupt request
TTREG6
INTTC6 interrupt request
TC6CR<TC6S>
TC6 pin input
Counter
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/2
Hz in the SLOW1/2 or SLEEP1/2 mode.
and the TTREGj value is detected, the logic level output from the
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
Note 3: j = 5, 6
This mode is used to generate a pulse with a 50% duty cycle from the
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
To use the programmable divider output, set the output latch of the I/O port to 1.
pulses.
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
?
Figure 11-3 8-Bit Event Counter Mode Timing Chart (TC6)
?
0
Figure 11-2 8-Bit Timer Mode Timing Chart (TC6)
n
n
1
1
2
3
2
Match detect
Match detect
n-1
Page 126
PDOj
n-1
n 0
n 0
pin. An arbitrary value can be set to the timer F/Fj by
Counter clear
4
Counter
clear
1
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
1
2
2
Match detect
PDOj
Match detect
PDOj, PWMj
n-1
pin is switched to the opposite state and
PDOj
n-1
n
and
n
0
pin.
0
Counter
clear
PPGj
1
Counter clear
1
pins may output
2
2
TMP86PM49UG
0
0
4