TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 126

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)
Table 10-5 PWM Output Mode
DV7CK = 0
fc/2
NORMAL1/2, IDLE1/2 mode
fc/2
fc/2
fc/2
11
fc/2
fs
up-counter counts up using the internal clock.
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
erated. Upon reset, the timer F/Fj is cleared to 0.
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immedi-
ately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
fc
7
5
3
[Hz]
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen-
(The logic level output from the
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
Note 2: When the timer is stopped during PWM output, the
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
Note 4: j = 3, 4
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter-
rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out-
put from the
Source Clock
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
fc/2
3
fs
fc
[Hz]
7
5
3
PWMj
pin during the warm-up period time after exiting the STOP mode.
PWMj
SLOW1/2,
SLEEP1/2
fs/2
mode
3
PWMj
fs
–
–
–
–
–
pin to the high level when the TimerCounter is stopped
[Hz]
PWMj
pin to the high level.
pin is the opposite to the timer F/Fj logic level.)
Page 109
fc = 16 MHz
30.5 µs
62.5 ns
128 µs
500 ns
125 ns
8 µs
2 µs
Resolution
PWMj
fs = 32.768 kHz
pin holds the output status when the timer is
244.14 µs
30.5 µs
–
–
–
–
–
fc = 16 MHz
32.8 ms
2.05 ms
7.81 ms
512 µs
128 µs
32 µs
16 µs
Repeated Cycle
TMP86PM49UG
fs = 32.768 kHz
62.5 ms
7.81 ms
–
–
–
–
–