TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 207

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

15.3 Function
(2)
(3)
SIO2RDB, SIO2SR<RXF> is cleared to “0”.
level by an automatic-wait function when all of the bit set in the data has been transmitted.
the received data from SIO2RDB, or reading the received data from SIO2RDB after writing the next
data to SIO2TDB.
Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.
In external clock operation, reading the received data from SIO2RDB and writing the next data to
SIO2TDB must be finished before the shift operation of the next data begins.
If the transmit data is not written to SIO2TDB after SIO2SR<TXF> is set to “1”, transmit error
occurs immediately after shift operation is started. When the transmit error occurred,
SIO2SR<TXERR> is set to “1”.
If received data is not read out from SIO2RDB before next shift operation starts after setting
SIO2SR<RXF> to “1”, receive error occurs immediately after shift operation is finished. When the
receive error has occurred, SIO2SR<RXERR> is set to “1”.
During the transmit/receive operation
When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0” and when a data is read from
In internal clock operation, in case of the condition described below, the serial clock stops to “H”
The automatic wait function is released by writing the next transmit data to SIO2TDB after reading
Stopping the transmit/receive operation
There are two ways for stopping the transmit/receive operation.
• Next transmit data is not written to SIO2TDB after reading a received data from SIO2RDB.
• Received data is not read from SIO2RDB after writing a next transmit data to SIO2TDB.
• Neither SIO2TDB nor SIO2RDB is accessed after transmission.
• The way of clearing SIO2CR<SIOS>.
• The way of setting SIO2CR<SIOINH>.
When SIO2CR<SIOS> is cleared to “0”, transmit/receive operation is stopped after all trans-
fer of the data is finished. When transmit/receive operation is finished, SIO2SR<SIOF> is
cleared to “0” and SO2 pin is kept in high level.
In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is
set to “1” by beginning next transfer.
Transmit/receive operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In
this case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are
initialized.
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TMP86PM49UG