TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 191

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

14.3 Function
SI1 pin
SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
SCK1
SO1 pin
INTSIO1
interrupt
request
SIO1SR<TXF>
SIO1TDB
SIO1SR<RXF>
SIO1RDB
pin output
Figure 14-14 Example of External Clock and MSB Transmit/Receive Mode
(4)
errors occur transmits or receives.
Writing transmit
data A
Transmit/receive error processing
Transmit/receive errors occur on the following situation. Corrective action is different, which
(a) Transmit errors
A
Transmit errors occur on the following situation.
• Shift operation starts before writing next transmit data to SIO1TDB in external clock op-
A7 A6
D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
eration.
If transmit errors occur during transmit operation, SIO1SR<TXERR> is set to “1” im-
mediately after starting shift operation. And INTSIO1 interrupt request is generated af-
ter all of the 8-bit data has been received.
If shift operation starts before writing data to SIO1TDB after SIO1CR<SIOS> is set to
“1”, SIO1SR<TXERR> is set immediately after starting shift operation. And INTSIO1
interrupt request is generated after all of the 8-bit data has been received.
SO1 pin is kept in high level when SIO1SR<TXERR> is set to “1”. When transmit error
occurs, transmit operation must be forcibly stop by writing SIO1CR<SIOINH> to “1”
after the received data is read from SIO1RDB. In this case, SIO1CR<SIOS>, SIO1SR
register, SIO1RDB register and SIO1TDB register are initialized.
Writing transmit data
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Reading received
data D
Writing transmit
data B
Reading received data
Page 174
D
B
Start shift
operation
Writing transmit
data C
Reading received
data E
E
C
Start shift
operation
Clearing SIOS
Reading received
data F
F
TMP86PM49UG