STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 2

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

STPC
DESCRIPTION
The STPC Atlas integrates a standard 5th
generation x86 core along with a powerful UMA
graphics/video chipset, support logic including
PCI, ISA, Local Bus, USB, EIDE controllers and
combines them with standard I/O interfaces to
provide a single PC compatible subsystem on a
single device, suitable for all kinds of terminal and
industrial appliances.
2/111
X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
Can access up to 4GB of external memory.
8Kbyte unified instruction and data cache
Parallel processing integral floating point unit,
Runs up to 133 MHz (X2).
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 2.5V operation.
SDRAM Controller
64-bit data bus.
Up to 90MHz SDRAM clock speed.
Integrated system memory, graphic frame
Supports 8MB up to 128 MB system memory.
Supports 16-Mbit, 64-Mbit and 128-Mbit
Supports 8, 16, 32, 64, and 128 MB DIMMs.
Supports buffered, non buffered, and
4-line write buffers for CPU to DRAM and PCI
4-line read prefetch buffers for PCI masters.
Programmable latency
Programmable timing for SDRAM
Supports -8, -10, -12, -13, -15 memory parts
Supports memory hole between 1MB and
32-bit access, Autoprecharge & Power-down
processor fully PC compatible.
with write back and write through capability.
with automatic power down.
memory and video frame memory.
SDRAMs.
registered DIMMs
to DRAM cycles.
parameters.
8MB for PCI/ISA busses.
are not supported.
®
ATLAS
Issue 1.0 - July 24, 2002
Enhanced 2D Graphics Controller
Supports pixel depths of 8, 16, 24 and 32 bit.
Full BitBLT implementation for all 256 raster
Supports 4 transparent BLT modes - Bitmap
Hardware clipping
Fast line draw engine with anti-aliasing.
Supports 4-bit alpha blended font for anti-
Complete double buffered registers for
64-bit wide pipelined architecture running at
CRT Controller
Integrated 135MHz triple RAMDAC allowing
8-, 16-, 24-bit pixels.
Interlaced or non-interlaced output.
Video Input port
Accepts video inputs in CCIR 601/656 mode.
Optional 2:1 decimator
Stores captured video in off setting area of
HSYNC and B/T generation or lock onto
Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Color space conversion (RGB to YUV and
Programmable window size.
Chroma and color keying for integrated video
operations defined for Windows.
Transparency, Pattern Transparency, Source
Transparency and Destination Transparency.
aliased text display.
pipelined operation.
90 MHz. Hardware clipping
for 1280 x 1024 x 75Hz display.
the onboard frame buffer.
external video timing source.
YUV to RGB).
overlay.